1. Field of the Invention
The present invention relates to a magnetic disk drive, and more particularly, to a serial interface circuit for adaptively supporting the serial interface of the read/write channel circuits of various standards.
2. Description of the Related Art
Recently the data storing and retrieving technique is rapidly and greatly improved to manufacture high-capacity and high-speed storage devices like hard disk drives widely employed as auxiliary storage devices for computer systems.
In the magnetic disk drives, the read/write channel circuit detects and decodes data pulses from read signals transmitted by the preamplifier coupled to heads so as to transfer the to the DDC (disk data controller) and conversely decodes write data from the DDC and supplies it to the preamplifier. When retrieving data, the preamplifier amplifies signals picked-up by the heads from the disks (recording medium) so as to supply them to the read/write channel circuit, and when recording data, selects a head in response to an instruction from the DDC so as to record the encoded write data received from the read/write channel circuit on the corresponding disk.
The read/write channel circuit controls the internal constituent circuits through an internal built-in serial port under the control of a central processing unit (CPU). Various states of a read/write channel circuit are transferred through the serial port to the CPU. Namely, the above serial port is a bidirectional port which serially interfaces between the read/write channel circuit and the CPU.
By way of example, a read/write channel circuit includes an ENcoder/DECoder(ENDEC) which decodes recording data and encodes synchronous reading data, a pulse and servo detector which detects amplitudes of bursts to generate position error signals and detects peak values of amplitudes of the preamplified signals, and a data separator which separates read data synchronized with specific clocks from data pulses generated by the pulse and servo detector, and further includes an automatic gain control (AGC) circuit, a programmable filter, a hysteresis qualifier, etc. Each of the internal circuits has respective registers for storing information used for operation controls of the corresponding circuit.
The built-in serial port in the read/write channel circuit has n number of serial port registers (hereinafter referred to as "state control registers"). For example, n number of state control registers are respective registers for setting power-down, data mode cut-off, servo mode cut-off, filter boost, data threshold value, servo threshold value, data restoring, and AGC level, etc. Each of the registers has a specific control value for setting the corresponding functions.
The CPU supplies the serial port control signals, i.e. SDEN, SDATA and SCLK, to the above serial port, where SDEN is a data transmission enabling signal, and SDATA is serial data of CPU, and SCLK is a serial clock signal. The SDATA carries the address for selecting the specified state control register of the serial port and the data for reading (or writing) the control state of the register selected by the above address. The address of the serial data includes the read/write selection bits for controlling the data reading and/or writing selections.
When the serial port control signal is supplied, the CPU accesses to the state control register according to the address in the serial data SDATA and reads (or writes) the control state from (or to) the register accessed according to the data in the SDATA. The read or write selection is performed according to the binary logic state of the read/write selection bit in the address. If the control state is written, the serial port loads the above control state on the corresponding internal circuit of the read/write channel circuit. If the control state is read, the serial port loads the current control state of the accessed state control register on the serial data SDATA to transfer it to the CPU.
Since the read/write channel circuit is packed in a single chip specially designed by manufacturers, it is natural that the bit numbers of the serial ports for interfacing between the read/write channel circuit and the CPU are different depending on manufacturers. The bit numbers of the serial ports are for example 16 bits, 18 bits and 8 bits which mean a variety of serial port implementations.
In order to serially interface between earlier read/write channel circuits of various standards and the CPU, the related control designs of the CPU or DSP (digital signal processor) must be modified by adapting to the bit number of the serial port of the read/write channel circuit. Accordingly, to remove such inconveniences, it is desired to devise a serial interface circuit adapting to the read/write channel circuits of various standards.
The patent to Daly et al., U.S. Pat. No. 4,071,887, entitled Synchronous Serial Data Adaptor, discloses an integrated circuit synchronous data adaptor for providing a bidirectional interface for a synchronous data interchange.
The patent to Hardie et al., U.S. Pat. No. 4,901,275, entitled analog Data Acquisition apparatus And Method Provided With Electro-Optical Isolation, discloses a unit for providing an interface between analog input signals and a digital data processing system bus.